1. Field of the Invention
The present invention relates to, for example, a semiconductor memory device, and more specifically, to a row decoder in which a high-voltage-applied portion is located adjacent to a low-voltage-applied portion while a write operation is being performed on a NAND type flash memory to which multivalued information can be written.
2. Description of the Related Art
A NAND type flash EEPROM (Electrically Erasable Programmable Read Only Memory) is known as a non-volatile semiconductor memory device. FIG. 18 is a functional block diagram schematically showing a general configuration of a NAND type flash EEPROM (semiconductor memory device). As shown in FIG. 18, this memory is provided with a memory cell array MCA and a row decoder RD. The row decoder RD has a transfer gate section TG and transfer gate control sections TCa and TCb all of which are used to apply voltages to word lines of a memory cell MC.
FIG. 19 schematically shows the memory cell array MCA in FIG. 18. As shown in FIG. 19, a first cell block CB1 of the memory cell array MCA has m NAND columns. Each of the NAND columns has memory transistors MT1 to MT2n connected in series and selection transistors ST1 and ST2. Each of the memory transistors is composed of a known transistor used in a flash memory, or MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor, or the like. For a write, charges are injected into a charge store film (a floating gate electrode). Gates of transistors belonging to the same row in each NAND column are connected together by control gates CGa1 to CGa2n, SGa1, and SGa2. A second cell block CB2 has a similar configuration. One of the selection transistors of each NAND column is connected to bit lines BL1 to BLm. The other is connected to a source line SL.
FIG. 21 schematically shows the transfer gate section TG in FIG. 18. As shown in FIG. 21, transfer gate transistors TRa1 to TRa2n are connected to transfer gate transistors TRb1 to TRb2n, respectively, at their corresponding first ends via connection sections N1 to N2n. Second ends of the transfer gate transistors TRa1 to TRa2n and the transfer gate transistors TRb1 to TRb2n are connected to control gates CGa1 to CGa2n and CGb1 to CGb2n, respectively. a1 to a2n and b1 to b2n correspond to row addresses.
In a semiconductor memory device having this configuration, when information is written to a memory cell MC1 located where the control gate CGa4 crosses the bit line BL2, a low level is first applied to the bit line BL2. On the other hand, a high level is applied to the other bit lines.
With an SB (Self Boost) method, which is commonly used to record binary information, a program voltage Vpg (for example, about 18V) is applied to the control gate CG4a. On the other hand, a pass voltage Vps (for example, about 10V) is applied to the other control gates. As a result, information is written to the memory cell MC1.
To apply the above voltages to the respective control gates, the program voltage Vpg is applied to a connection section N4, while the pass voltage Vps is applied to the other connection sections. Then, an on-voltage Vpgh (=Vpg+a threshold voltage for the transistors) is applied to the gate wire Ga1. As a result, the transfer gate transistors TRa1 to TRa2n are turned on. The voltages at the connection sections N1 to Nn are transferred to the control gates CGa1 to CGan, respectively. At this time, 0V is applied to the gate wire Gb1. Accordingly, the voltages at the connection sections N1 to Nn are not transferred to the control gates CGb1 to CGbn.
When the voltages are applied to the connection sections and word lines, respectively, a parasite transistor is formed between the transfer gate transistors TRa4 and TRa3 (or Tra5) wherein the pass voltage Vps, the program voltage Vpg, and the on-voltage Vpgh are applied to its source, drain, and gate, respectively. However, with such a combination of voltages, a so-called back bias effect is produced to suppress a leak current flowing through the parasite transistor.
Recently, multivalued information is recorded in memory cells. In this case, an LSB (Local Self Boost) method is used to write information. With the LSB method, the program voltage Vpg is applied to the control gate CGa4. Zero V is applied to the control gates CGa3 and CGa5. The pass voltage Vps is applied to the other control gates. When these voltages are applied, a parasite transistor is formed between the transfer gate transistors TRa4 and TRa3 (or Tra5) wherein 0V, the program voltage Vpg, and the on-voltage Vpgh are applied to its source, drain, and gate, respectively. Then, a large leak current flows through this parasite transistor. Thus, to prevent adjacent transfer gate transistors from having such a combination of voltages, the transfer gate section properly determines how to arrange the transfer gate transistors.
Further, an EASB (Erased Area Self Boost) method may be used in place of the LSB method. With the EASB method, 0V is applied to the control gate CGa5, located adjacent to the control gate CGa4 and closer to a source line. On the other hand, the pass voltage Vps is applied to the other control gates.
As described above, with the LSB method or the EASB method, the transistors can be properly arranged so as to prevent a transfer gate transistor to which 0V is applied from lying adjacent to a transfer gate transistor to which the program voltage Vpg is applied. However, even in this case, it is unavoidable that a transfer gate transistor to which 0V is applied is located adjacent to a transfer gate to which the pass voltage Vps is applied. Thus, a parasite transistor is formed between these transistors wherein 0V, the pass voltage Vps, and the on-voltage Vpgh are applied to its source, drain, and gate, respectively. As a result, the conductivity of an element separating insulating film in this portion is inverted to cause a large leak current to flow.
It is contemplated that the concentration of impurities in an area under an element separating insulating film between transfer gate transistors may be increased in order to suppress a leak current flowing through a parasite transistor (in order to increase an inverse withstanding voltage). However, increasing the concentration of impurities in this area reduces the junction withstanding voltage of the transfer gate transistors.
On the other hand, the leak current can be reduced by using a larger element separating insulating film between the transistors. However, the larger element separating insulating film contributes to increasing the area of the transfer gate section. This hinders a semiconductor memory device based on the LSB or EASB method from having a fine-grained structure.